It is well known that digital-to-analog converters (DAC) introduce amplitude distortion into the frequency spectrum of a signal being converted. This property is described in H. Samueli, “The design of multiplierless FIR filters for compensating D/A converter frequency response distortion,” IEEE Trans. Circuits and Systems, vol. 35, no. 8, pp. 1064-1066, August 1988 [Samueli], which is herein incorporated by reference in its entirety. Moreover, a commonly-employed remedy for this distortion is the preprocessing of the digital signal by a discrete-time transfer function before it enters the DAC. This transfer function performs an alteration of the input signal's frequency spectrum that approximates the opposite, or inverse, of the amplitude distortion operation the DAC performs, thereby tending to cancel the effects of the DAC distortion.
As further evidenced by Samueli, it is well known that the distortion introduced by a DAC can be described by a transfer function involving a sinc function in the following mannerHD/A(f)=sin c(πf/fs)e−jπf/fs where sinc(x)=sin(x)/x and fs=1/T is the sampling rate of the DAC. The discrete-time transfer function that compensates for the DAC distortion is often referred to as an “inverse-sinc” function and is typically implemented by a simple system that takes the form of an FIR digital filter. It is common, therefore, to also find such a transfer function referred to as an inverse-sinc filter. The simple seven-tap linear-phase FIR filter shown in FIG. 2 depicts one exemplary implementation of an inverse-sinc filter. Further examples of inverse-sinc filters, including the filter of FIG. 2, are given in Samueli.
In application, inverse-sinc filters are often preceded by high-speed systems. One method of constructing certain high-speed digital systems, while employing digital technology that does not operate efficiently at the desired high speed, is to construct multiple copies of the digital system and operate them simultaneously, in parallel, at a lower speed. The outputs of these parallel systems are then interleaved with one another. Examples of such interleaved structures can be found in L. K. Tan, E. Roth, G. E. Yee, and H. Samueli, “An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS,” in Proc. IEEE International Solid-State Circuits Conf., Feb. 17, 1995, pp. 258-259 [Tan]; R. Hassun and A. W. Kovalick, “Waveform synthesis using multiplexed parallel synthesizers,” U.S. Pat. No. 4,454,486., Jun. 12, 1984 [Hassun]; and K. Gentile, “Parallel-process digital modulator structures and methods,” U.S. Pat. No. 6,621,366 B1., Sep. 16, 2003 [Gentile], all of which are incorporated herein by reference.
In one example, the interleaving of two parallel systems' outputs can be performed by a digital multiplexer (MUX) having two inputs and a single output. The MUX output value is always one of the two input values, as determined by the 0/1 setting of an input control signal that is supplied to the MUX. By switching the control signal back and forth between 0 and 1 at a high frequency f, it becomes possible to interleave two systems' outputs, creating an output sequence at the high frequency f, while each of the two systems operates at the lower frequency f/2. Only the actual MUX circuitry needs to operate at the high frequency f.
Similarly, by operating four sub-systems in parallel, as described in Tan, and employing a four-to-one MUX, it becomes possible to create a system that interleaves the four sub-system outputs into a single output signal having a high-speed data rate f, while each sub-system operates at the four-times lower frequency f/4. The 4-to-1 MUX sequentially couples the four sub-system output signals to the output of the MUX and then repeatedly continues this sequential coupling.
The performance of an inverse-sinc filtering operation on a high-speed signal can be problematic. For example, consider a high-speed system that has been constructed by interleaving the outputs of multiple sub-systems, wherein the resulting high-speed digital signal created is supplied to a DAC. It appears necessary to build an FIR filter that operates at the high data rate of the interleaved signal, since it is not possible to do the filtering by including separate copies of the inverse-sinc filter within each of the sub-systems. That is, the filtering cannot be performed on each sub-system's individual output, since the interleaving (MUXing) of such filtered outputs would yield a quiet different result than the desired result—i.e., the filtering of the interleaved sequence.
In principle, a feed-forward system, such as an FIR filter, can be operated at an arbitrarily high data rate. It is well known that pipeline stages can be incorporated into a feed-forward system, and, by inserting enough such pipeline stages, virtually any desired high data rate can be achieved. However, the overhead cost of such high-speed pipeling hardware can be prohibitive. This cost can be expressed in terms of an increase in the system's power dissipation, an increase in integrated-circuit area, an increase in system complexity, and ultimately, actual monetary cost of system fabrication and/or operating cost.
What is therefore needed are new systems and methods for implementing inverse-sinc filters, or equivalents thereof, that can efficiently process signals produced by high-speed systems.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.